OLIX has raised $312 million to develop an alternative architecture for running large artificial intelligence models, giving the two-year-old London semiconductor company a $3.3 billion valuation before its first production systems have reached customers.

The Series B round included new backing from Fundomo, Arm, and Hudson River Trading, while existing investors Hummingbird Ventures, Crane, Plural, Creandum, Phoenix Court, and Transition increased their commitments. OLIX has also appointed networking researcher and entrepreneur Professor Nick McKeown to its board, alongside Matt Briers, the former Wise finance chief, as chief financial officer.

Rather than designing another general-purpose accelerator, OLIX is building a collection of specialist chips for different stages of AI inference — the process through which a trained model handles an input and produces an answer. Its X-1 platform distributes a model across many chips, with an optical interconnect moving information between them using light rather than conventional copper connections.

The first component, known as DX-1, is being designed for the decode stage in which a model generates its output one token at a time. OLIX plans to deliver the accelerator to its first customers during the second half of 2027, using the financing to fund chip development, manufacturing commitments, and engineering recruitment.

Inference creates a different hardware problem

Most attention around AI infrastructure initially fell on training, since creating a large model requires enormous clusters of processors working for extended periods. However, the economic balance changes after deployment because every subsequent query consumes computing capacity, memory bandwidth, electricity, and data-centre space.

Those inference costs accumulate as models serve millions of users or become embedded in software, search, customer service, engineering, and automated workflows. A model that appears commercially acceptable during a pilot can become expensive once response volumes increase, particularly where customers expect low latency and suppliers cannot group requests into large processing batches.

OLIX argues that current hardware treats the process too uniformly, running operations with different requirements on the same general-purpose processors. Its proposed alternative resembles a production line, with particular chips handling defined parts of the workload while retaining enough programmability to accommodate changes in model design.

That approach may improve efficiency, although it also creates engineering and commercial risks. A distributed system must coordinate a model across numerous components without adding delays, while the compiler, networking, memory, packaging, and silicon must operate as a coherent platform rather than as individually impressive parts.

The company says its “slow and wide” optical interconnect will move information directly between chips at low latency and energy cost. It also intends to store model data in on-chip SRAM, avoiding the high-bandwidth memory and advanced packaging components that have become constrained parts of the AI hardware supply chain.

Avoiding scarce components could make production easier, but only if the architecture can be manufactured reliably and supported at the volumes customers require. Semiconductor businesses must secure fabrication capacity, packaging, testing, boards, optical components, racks, power systems, and maintenance arrangements long before revenue begins to resemble the capital invested.

Software will decide whether the system travels

Hardware performance alone will not persuade model developers and cloud providers to change platforms, since much of the AI software ecosystem has been optimised around established accelerators. Customers will expect models, development tools, monitoring, orchestration, and production applications to run without extensive rewriting.

Consequently, OLIX’s compiler may prove as important as the chips themselves. It is intended to schedule workloads deterministically across racks, which could help manage the complexity of splitting a model across specialised components, although the company will need to demonstrate that this works across changing architectures and real customer workloads.

The first deployments will also reveal whether the platform performs well outside carefully selected benchmarks. Model size, input length, output length, concurrency, latency targets, power use, and the balance between prefill and decode can all alter the economics of inference, making a single performance figure a poor substitute for sustained production evidence.

OLIX claims DX-1 can produce more than 10,000 tokens per second for each user on a 100-billion-parameter model while improving output per watt. That remains a company projection rather than an independently verified production result, and prospective customers will want to test performance, reliability, and cost against their own models before committing infrastructure budgets.

The appointments accompanying the funding suggest OLIX is preparing for that transition. McKeown brings experience in software-defined networking and programmable infrastructure, while Briers built Wise’s finance operation through its expansion and London listing. Both roles become more consequential as a research-led semiconductor company moves towards manufacturing, customer contracts, and a longer-term capital strategy.

Britain has produced influential processor designs and semiconductor research, but relatively few domestic companies have built large AI computing platforms. OLIX therefore adds a potentially significant hardware business to the country’s AI ecosystem, although its prospects cannot be assessed from valuation or investor names alone.

By the time the first DX-1 systems reach customers in 2027, established chipmakers will also have advanced their products, software, memory systems, and interconnects. OLIX’s opportunity rests on whether specialisation can improve the cost of inference faster than incumbent platforms improve, without replacing one infrastructure bottleneck with several new ones.