Germany and the Netherlands are putting artificial intelligence to work on one of Europe’s more persistent semiconductor bottlenecks, launching a joint programme intended to shrink the time needed to design advanced AI chips from years to weeks.

Germany’s Federal Agency for Breakthrough Innovation, SPRIND, and the Netherlands’ National Agency for Disruptive Innovation, or NADI, are collaborating on the 20-month AI-Native Chip Design Challenge. Rather than using machine learning as an auxiliary engineering tool, the programme is seeking teams capable of applying AI across semiconductor architecture, RTL generation, verification, and optimisation.

SPRIND says individual teams can receive up to €9.6 million across two stages, comprising as much as €2.6 million during an initial eight-month phase and a further €7 million over the following 12 months. Reuters has reported an overall €40 million commitment from the two agencies, while the strongest projects could later receive additional funding to move completed designs through tape-out.

The agencies are asking teams to develop high-performance, energy-efficient architectures for AI workloads, including systems intended for Europe’s planned AI gigafactories as well as applications spanning data security, biotechnology, robotics, and mobility. Applications remain open until 30 November.

Although Europe already occupies important positions in the semiconductor supply chain, particularly through Dutch lithography equipment and specialist research organisations, the boom in generative AI has exposed a different weakness. Much of the computing used to train and run the largest models still depends on accelerator architectures and software ecosystems developed elsewhere, while AI workloads are changing more quickly than conventional semiconductor development cycles can comfortably follow.

Chip design becomes an AI workload

SPRIND and NADI are therefore attacking the design cycle itself, with reinforcement learning, autonomous agents, and other AI systems expected to search architectures, generate hardware descriptions, carry out verification work, and navigate engineering trade-offs with less manual intervention. If those systems can reduce iteration times without weakening verification, smaller specialist teams could test architectures that would previously have required much larger engineering organisations and longer development budgets.

There is an important distinction between using AI to improve an established electronic-design-automation tool and allowing software agents to take responsibility for a much larger part of the engineering process. The latter could alter both the economics of specialist chip development and the number of teams capable of attempting it, provided the resulting designs survive the less forgiving stages that follow.

Semiconductor development is expensive partly because errors become progressively more costly as a design approaches fabrication. A software fault can usually be corrected and redeployed, whereas a flaw discovered after a chip has been manufactured can consume months of work and substantial fabrication expenditure, leaving verification as a central part of the challenge rather than an administrative step that can simply be automated away.

The agencies also want production-ready designs rather than simulated demonstrations, which pushes the programme beyond a research exercise. Successful chips will still require fabrication capacity, advanced packaging, memory, boards, drivers, compilers, developer tools, and customers prepared to adopt them.

That path from architecture to commercially useful hardware is already visible elsewhere in Europe’s AI-chip market. Dutch company Axelera AI, for example, has been moving its European inference accelerator into partner systems, illustrating how much engineering and ecosystem work remains after the chip itself has been designed.

Industrial policy moves further upstream

Governments have spent years using subsidies, research funding, procurement, and manufacturing incentives to increase semiconductor capacity, but the new challenge places public money earlier in the development cycle and gives competing teams defined engineering objectives rather than subsidising a predetermined industrial asset.

NADI itself is new, having been established by the Dutch government with €500 million in funding, while Germany has used SPRIND to support projects that conventional research grants or venture investors may consider too technically uncertain. Their first joint programme therefore becomes a test of whether national innovation agencies can work across borders around technologies where a domestic market alone is unlikely to provide enough scale.

Semiconductors are particularly suited to that approach because national supply chains are largely fictional. European chip development already depends on equipment, research, intellectual property, design expertise, manufacturing, and packaging distributed across several countries, while the eventual customers may sit elsewhere again.

If the challenge produces viable architectures, tape-out will become the next decisive test. SPRIND and NADI have acknowledged that step by signalling follow-on funding for the strongest teams, although moving from an AI-generated design to repeatable silicon will reveal whether the promised acceleration survives foundry rules, physical verification, manufacturing constraints, and production economics.

The programme will not produce European semiconductor independence on its own, but it could shorten one of the industry’s slowest development stages. With AI models and workloads changing on far shorter cycles than hardware, reducing the gap between a new computing requirement and the chip designed to meet it would itself be a useful industrial capability.